1. Field of the Invention
This invention relates to computer systems, and more particularly, to data transmission between various units of a computer system.
2. Description of the Related Art
Computer systems typically include a several chips for the purpose of data transmission to and from peripheral devices. FIG. 1 is a block diagram of one embodiment of a peripheral controller chip. A typical peripheral controller chip includes various functional units. Such functional units may include a microcontroller/CPU, a serial interface engine (SIE), one or more peripheral interfaces, a memory management unit (MMU) and a direct memory access controller (DMAC) associated with each interface. The microcontroller/CPU may be a simple (and sometimes low-speed) processor which manages the data flow within the chip from one interface to another. The SIE may include logic that translates a data format between a serial data stream of a serial bus to a parallel data stream internal to the chip. Similarly, any peripheral interface may perform data translations between a format suitable for the peripheral bus and the format of data internal to the chip. The MMU may include a FIFO (first-in first out) memory, as in the embodiment shown, or a dual-ported static random access memory (SRAM) in other embodiments. The FIFO or the SRAM of the MMU may provide temporary storage for data being transmitted between two interfaces to allow rate adaptation and/or flow control between the interfaces. A DMAC associated with each interface may control data transfers between the MMU and the various external interfaces. The chip may also include an internal address and data bus to accommodate the data transfers internal to the chip.
Such devices as the one described above may experience significant delays and latencies during their operation. Each functional unit transmitting data internal to the chip must first acquire control of the internal data and address buses. Thus, other functional units needing to transmit and/or receive data may be delayed until the buses are released. The process of acquiring and releasing the bus by each of the functional units may slow down the movement of data through the chip. This may also result in more demanding processing requirements for the microcontroller/CPU. As a result, many such chips may not be suitable for use in systems that require high-speed data movement. Furthermore, since the bandwidth of the FIFO or SRAM (i.e. the ability to read from or write to) is much greater than the required bandwidth for data transmissions between one functional unit and another, MMU utilization may be very inefficient.
Another performance issue may deal with the type of data being transmitted. In some cases, the data being transferred between two function units may include commands, which may need to be intercepted and interpreted by the MCU/CPU.
In addition to the performance drawbacks, such chips may be expensive to implement. In particular, the need for DMACs may significantly increase the cost of a given device. Such devices may also require a bus arbiter in order to arbitrate access to the internal buses. Adding a bus arbiter may further add to both the complexity and expense of such a device, as well as increasing the complexity of other logic that must interface with the bus arbiter. A FIFO memory that may be employed in some embodiments may consume a significant amount of chip area.
In general, many such devices with greater logic complexity may be more costly to implement and yet still may not meet the requirements for high-speed data transmission.